As linear dimensions continue to decrease on integrated circuits, interconnections between components become increasingly difficult. Metal layers are frequently used as interconnections for signal routing and for power bus distribution. In many instances, decreasing linear dimensions of such a metal layer may increase the intrinsic time constant associated with these interconnect lines, thereby impairing response times for the circuit. Also, fringing capacitance increases whenever these metal lines are placed closer to each other. Since minimum spacing between lines is almost always used, this further increases the intrinsic time constant associated with these lines.
Power bus distribution lines are usually very wide and consume large amounts of area on the integrated circuit. For example, power bus distribution lines usually must be slotted when they are routed around corners, so that shear stresses resulting from the interface between the metal line and compressive nitride protective overcoat may be prevented from moving the metal line and causing a failure. When metal lines are slotted, even more surface area is required to achieve the same amount of resistance per unit length for the bus.
Therefore, a need has arisen for a method and structure of interconnect in an integrated circuit which decreases linear dimensions of the integrated circuit without significantly impairing circuit performance.